SDD 2007 - Call for Participation

CALL FOR PARTICIPATION

Scope and Mission --Program Overview -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope and Mission

Troubleshooting how and why systems and circuits fail is important and is rapidly growing in industry significance. Debug and diagnosis may be needed for yield improvement, process monitoring, correcting the design function, failure mode learning for R&D, or just getting a working first prototype. This detective work can however become very tricky. Sources of difficulty include circuit and system complexity, packaging, limited physical access, shortened product creation cycle and time-to-market, the traditional focus on only pass/fail testing and missing tool and equipment capabilities. New and efficient solutions for debug and diagnosis will have a much needed and highly visible impact on productivity. The mission and objective of the SDD’07 Workshop is to consider all issues related to debug and diagnosis of systems and circuits – from prototype bring-up to volume production.

Program Overview

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The SDD’07 Advance Program is printed on the back of this Call for Participation. This high-quality program covers an entire range of silicon debug and diagnosis topics, with presenters providing details of their recent results on fault diagnosis, process debug, micro-processor debug, and system-level debug. This year there is a special session on the application uses of FPGAs and configurable logic for debug and diagnosis, and a panel of debug experts to explore and discuss the possibilities for fostering further collaboration between the industry, tool vendors, and academia in the field of silicon debug and diagnosis.

Workshop Registration

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Online registration for SDD’07 is now open. Go to SDD'07 Online Registration for more details.

Advance Program

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Wednesday -- Thursday

May 23 , 2007 (Wednesday)

4:15 PM - 5:15 PM	Opening Session
4:15 - 4:30	Opening Remarks Rob Aitken - ARM; Bart Vermeulen - NXP Semiconductors
4:30 - 5:15	Keynote Rolf Kuehnis - Nokia

5:15 PM - 5:30 PM BREAK

5:30 PM - 6:45 PM	Session 1: Microprocessor Debug and Fault Diagnosis
	Hybrid Debug Technique for BIST Debug of Embedded SRAM in Café Microprocessor Rajesh Pendurkar - Sun Microsystems
	Layout and Implementation Advancements of Design for Debug Features on Next Generation Microprocessors John Giacobbe, Richard Livengood, Scot Zickel, Paul Hotchkiss - Intel
	Fault Diagnosis using Quantified Boolean Formulas Hratch Mangassarian, Andreas Veneris - University of Toronto; Marco Benedetti - University of Orléans

7:00 PM - 9:00 PM SOCIAL EVENT

May 24, 2007 (Thursday)

8:30 AM - 9:45 AM	Session 2: System-level Debug
	Scan Chain Based Functional Debugging Jouni Riihimäki, Pasi Kolinummi, Mika Koikkalainen, Jouko Skog - Nokia
	A new Debug Methodology for Efficient Use of Resources offered by Complex On-Chip Debug Solutions Josef Schicker, Christian Lipsky - IPextreme; Jens Braunes, Stefan Weisse - pls Development Tools
	A Run-time Memory Protection Approach for Multitasking Systems G.N. Gopakumar, Bart Vermeulen - NXP Semiconductors

9:45 AM - 10:10 AM	Highlights of the Debug Standardization Workshop at DATE 2007
	Adam Morawiec - ECSI

10:10 AM - 10:25 AM BREAK

10:25 AM - 11:55 AM	Panel 1: Fostering collaboration between the industry, tool vendors, and academia
Panelists:	Wu-Tung Cheng - Mentor Graphics Mike Genden - IBM Yu-Chin Hsu - Novas Matteo Sonza Reorda - Politecnico di Torino Hans-Joachim Wunderlich - University of Stuttgart

12:00 NOON - 1:00 PM LUNCH

1:00 PM - 2:40 PM	Session 3: Process Debug
	Design marginalities: Increasing focus of first-silicon validation, debug, and diagnosis Sandeep K. Gupta - University of Southern California, LA
	Circuit Edit continues to provide increased value in post-silicon debug at each process node Siegfried Pauthner, André Kabakow - Infineon; Donato Di Donato, Tahir Malik, Didier Renard - Credence
	New Circuit Edit and Probing Options directly to FET Device on Ultra Thin Silicon Backside processed by Focused Ion Beam Rudolf Schlangen, Uwe Kerst, Christian Boit - Berlin University of Technology
	Dynamic Optical Circuit Analysis for IC Design Debug Félix Beaudoin, Jean-Philippe Roux - Credence, Kevin Sanchez, Philippe Perdu - French Space Agency

2:40 PM - 2:55 PM BREAK

2:55 PM - 4:05 PM	Session 4: Special Session on FPGAs and Debug
	We're on the board… what now? Solving the Visibility issue in FPGA Prototyping Mario Larouche, Doug Amos - Synplicity
	Programmable Logic Core Based Post-Silicon Debug For SoCs" Bradley Quinton, Steven Wilton - University of British Columbia
	Exploring Infrastructure IPs to Enhance Configurable Logic Reliability Lorenzo Calì, Stefania Stucchi, Marco Scipioni, and Stefano Pucillo - STMicroelectronics

4:05 PM - 4:30 PM	Wrap-up
	Closing Remarks Rob Aitken - ARM; Bart Vermeulen - NXP Semiconductors

More Information

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For general information contact:

R. Aitken - General Chair
ARM
141 Caspian Court
Sunnyvale, 94089 CA, USA
Phone: +1 408 548 3297
Email: rob.aitken@arm.com

For program information contact:

B. Vermeulen - Program Chair
NXP Semiconductors
High Tech Campus 5
5656 AE Eindhoven, The Netherlands
Phone: +31 40 2749367
Email: bart.vermeulen@nxp.com

Committees

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General Chair
R. Aitken – ARM

Program Chair
B. Vermeulen – NXP Semi.

Past Program Chair
F. Muradali – National Semi

Special Session Chair
N. Nicolici – McMaster U.

Finance Chair
M. Ricchetti – AMD

Arrangements Chair
S. Goel – Novas

Local Arrangements
S. Disch – U. Freiburg

Electronic Media
I. Bayraktaroglu – Sun

Program Committee
M. Abramovici – DAFCA
D. Appello – ST Microelectronics
C. Boit – TU Berlin
W-T Cheng – Mentor Graphics
B. Cory – nVidia
A. Crouch – Inovys
J. Figueras – U. Barcelona
D. Gizopoulos – U. Piraeus
I. Hartanto – Xilinx
K. Hatayama – STARC
Y-C. Hsu – Novas
D. Josephson – Intel
R. Kapur – Synopsys
H. Kerkhoff – U. Twente
C. Landrault – LIRMM
T. McLaurin – ARM
C. Metra – U. Bologna
Y. Okuda – Sony
A. Orailoglu – UCSD
P. Prinetto – Poli. Di Torino
M. Renovell – LIRMM
M.S. Reorda – Poli. Di Torino
N. Stollon – First Silicon Solutions
C. Sul – Silicon Image
J. Tyzer – U. Poznan
S. Venkataraman – Intel
B. West
H. Wienrich – National Semi.

Steering Committee
R. Aitken – ARM
F. Muradali – National Semi.
E.J. Marinissen – NXP Semi.
M. Ricchetti – AMD (chair)
T. W. Williams – Synopsys
Y. Zorian – Virage Logic

For more information, visit us on the web at: http://evia.ucsd.edu/conferences/sdd/07

The 4th IEEE International Workshop on Silicon Debug and Diagnosis (SDD'07) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).